Without limiting the scope of the invention, its background is described in connection with the manufacture and formation of integrated circuit components for use in the creation of metal oxide semiconductors, as an example.
Heretofore, in this field, the major steps in silicon wafer fabrication have been the use of diffusion, metallization, etching and chemical clean-up steps to form semiconductors. The introduction of thermal oxidation of silicon, the use of lithographic photoresist techniques and etching of the various components using specific and non-specific chemical agents brought forth the era of the planar processing of semiconductor integrated circuits.
More recently, complementary metal oxide silicon devices (CMOS) have been formed by the growth, deposition and etching of conductive and non-conductive layers taking advantage of chemical-vapor deposition (CVD) and ion implantation techniques. Chemical vapor deposition allowed for the selective and non-selective deposition of, e.g., etch protective overcoats, and of masking material.
In addition to CVD, other common ways for the deposition of conducting or insulation thin films has been the use of vacuum deposition or sputtering. Vacuum deposition and sputtering coat the wafer with a thin film which can, e.g., form an inorganic insulating material when heated in a reactive atmosphere. All three techniques can be used to achieve the deposition of a conducting or insulating layer. The deposited layers may also be used as sacrificial layers for use in the selective etching and formation of an integrated circuit component.